1. Field of the Invention
The present invention relates to an analog buffer, and more particularly, to an analog buffer and a liquid crystal display apparatus using the same and a driving method thereof capable of reducing power consumption.
2. Discussion of the Related Art
A liquid crystal display device displays a picture by way of controlling a light transmittance of liquid crystal materials having a dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a drive circuit for driving the liquid crystal panel.
As illustrated in FIG. 1, the liquid crystal display device of the related art includes a liquid crystal panel 2r having a pixel matrix, a gate driver 4r for driving gate lines GL1 to GLn of the liquid crystal panel 2r, a data driver 6r for driving data lines DL1 to DLm of the liquid crystal panel 2r and a timing controller 8r for controlling a driving timing of the gate driver 4r and the data driver 6r. 
The liquid crystal panel 2r includes the pixel matrix having pixels 12r formed at each area defined by each intersection of gate lines GL and data lines DL. Each of the pixels 12r has a liquid crystal cell Clc that controls a light transmittance depending on the electric field generated by a pixel signal and a thin film transistor TFT that drives the liquid crystal cell Clc.
When the thin film transistor TFT receives a gate driving signal from a gate line GL, i.e., a gate high voltage VGH, the thin film transistor TFT is turned on to supply a video signal from the data line DL to the liquid crystal cell Clc. Moreover, when the thin film transistor TFT receives a gate low voltage VGL from the gate line GL, the thin film transistor TFT is turned off, thereby maintaining a video signal charged to the liquid crystal cell Clc.
The liquid crystal cell Clc can be equivalently represented as a capacitor. The liquid crystal cell Clc includes a common electrode and a pixel electrode connected to the TFT wherein a liquid crystal material is inserted between the common electrode and the pixel electrode. The liquid crystal cell Clc further includes a storage capacitor (not illustrated) for stably maintaining the video signal charged thereto until a next video signal is charged. The liquid crystal cell Clc varies the arrangement of liquid crystal materials with a dielectric anisotropy in accordance with the video signal charged through the TFT, thereby controlling the light transmittance. Accordingly, the liquid crystal cell Clc represents gray levels.
The liquid crystal panel 2r is driven by an inversion system in which a polarity of the liquid crystal cell Clc is inverted in a designated unit by a certain unit using a data signal, to prevent a deterioration of the liquid crystal materials and to improve display quality. The inversion system uses a frame inversion in which a polarity of a liquid crystal cell is inverted by units of one frame, a line inversion in which a polarity of a liquid crystal cell is inverted in units of horizontal lines, a column inversion in which a polarity of a liquid crystal cell is inverted in units of vertical lines, and a dot inversion in which a polarity of a liquid crystal cell is inverted in units of liquid crystal cells.
Among these inversion systems, the line inversion system has reduced power consumption compared to the column inversion and the dot inversion systems. It is because the column inversion and the dot inversion systems invert a polarity of a liquid crystal cell by using only a data signal, and thus a range of their driving voltages is relatively large, whereas, because the line inversion system alternates a common voltage Vcom supplied as a reference voltage, the range of a driving voltage can be lowered.
The gate driver 4r shifts a gate start pulse (GSP) from a timing controller 8r in accordance with a gate shift clock (GSC) to sequentially supply a scan pulse of the gate high voltage VGH to the gate lines GL1 to GLm. Moreover, the gate driver 4r supplies the gate low voltage VGL during a scan pulse of the gate high voltage VGH is not supplied to the gate lines GL1 to GLm.
The data driver 6r shifts a source start pulse (SSP) from the timing controller 8r in accordance with a source shift clock (SSC) to generate a sampling signal. Further, the data driver 6r latches a video data RGB provided by the signal SSC in accordance with the sampling signal, and then supplies the latched video data by a line unit in response to a source output enable (SOE) signal. Then, the data driver 6r converts digital video data RGB supplied by the line unit to analog video signals using gamma voltages, supplied from a gamma voltage, to thereby supply the analog video signals to the data lines DL1 to DLm. At this time, the data driver 6r determines the polarity of the video signals, in response to the polarity controlling signal (POL) from the timing controller 8r at the time of the conversion of the digital video data to the analog video signals.
The timing controller 8r generates the signals GSP and GSC for controlling the gate driver 4r, and also generates a source start signal SSP, a source shift clock SSC, a source output enable signal SOE and the signal POL signals for controlling the data driver 6r. More specifically, the timing controller 8r generates a variety of control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, POL and the like by using a data enable DE signal representing an effective data interval, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync and a dot clock (DCLK) to determine the transmission timing of the pixel data RGB.
In the liquid crystal display device configured as described above, the data driver 6r includes an analog buffer for preventing a distortion of the video signal supplied to the data line, in accordance with an amount of RC load on the data line. The gate driver 4r also includes an analog buffer for preventing a distortion of the gate driving signal supplied to the gate line, in accordance with an amount of RC load on the gate line. In general, an amplifier (OP-AMP) is mainly used for the analog buffer. However, a scheme having a simplified circuit configuration using an inverter has been recently proposed.
For instance, a paper “AMLCD '02”, pp. 21-24, published by Toshiba describes an analog buffer, which employs three inverters as illustrated in FIG. 2. The analog buffer illustrated in FIG. 2 includes: first to third inverters 3, 5 and 7 which are connected in series between an input line and an output line; first to third capacitors 2, 4 and 6 which are connected in series to input terminals of the first to the third inverter 3, 5 and 7, respectively; a first switch 1 connected between the input line and the first capacitor 2; second to fourth switches 8, 9 and 10 which are connected between input terminals and output terminals of the first to the third inverters 3, 5 and 7, respectively; and a fifth switch 11 connected between the input line and the output line.
First, for a reset interval RESET supplied by a first control signal CS1 as illustrated in FIG. 3, first to fourth switches 1, 8, 9 and 10 are turned on. Accordingly, an input terminal and an output terminal of the first to the third inverters 3, 5 and 7, respectively, are shorted, so that the first to third inverters 3, 5 and 7, respectively, are initialized to an inverter logic threshold voltage (VTH) at an intermediate voltage of a power voltage. Thus, the first to the third capacitors 2, 4 and 6, respectively, connected to each input terminal of the first to the third inverters 3, 5 and 7, are charged by a difference voltage of the input voltage Vin and the inverter logic threshold voltage VTH.
Next, for a feedback interval FEEDBACK, by a second control signal CS2 supplied as illustrated in FIG. 3, a fifth switch 5 for feedback is turned on, so that an output voltage Vout corresponding to the input voltage Vin is monitored in an output line. In other words, if a fed-back output voltage Vout is higher than the input voltage Vin when the fifth switch 11 is turned on, then the input voltage becomes higher than the threshold voltage VTH. As a result, the first to the third inverters 3, 5 and 7 drop the output voltage. If the fed-back output voltage Vout is lower than the input voltage Vin, then the input voltage Vin becomes lower than the threshold voltage VTH. As a result, the first to the third inverters 3, 5 and 7 raise the output voltage Vout. As described above, the output voltage Vout in the first to the third inverters 3, 5 and 7 is subject to an oscillation at an early stage of the feedback interval FEEDBACK, and ultimately converges to the input voltage Vin.
Because the analog buffer is organized with only the inverters, its configuration is simple compared to the related art analog buffer implemented using the amplifier OPAMP. However, in the analog buffer illustrated in FIG. 2, since the third inverter 7 in the output terminal should drive a data line DL with a large capacitance C, it has a drawback that its size should be large. Also, since the third inverter 7 in the output terminal should always maintain the threshold voltage VTH after the output voltage has been converged to the input voltage Vin, it has a drawback that its power consumption becomes large.